Exploring Adaptive Cache for Reconfigurable VLIW Processor
نویسندگان
چکیده
منابع مشابه
The Delft Reconfigurable VLIW Processor
In this paper, we present the rationale and design of the Delft reconfigurable and parameterized VLIW processor called ρ-VEX. Its architecture is based on the Lx/ST200 ISA developed by HP and STMicroelectronics. We implemented the processor on an FPGA as an open-source softcore and made it freely available. Using the ρ-VEX, we intend to bridge the gap between general-purpose and application-spe...
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This paper presents the architectural design of a reconfigurable and extensible Very Long Instruction Word (VLIW) processor. In addition to architectural extensibility, our processor also supports reconfigurable operations. Furthermore, we present an application development framework to optimally exploit the freedom of reconfigurable operations. Because our processor is based on the VEX ISA, we...
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Recently reconfigurable devices such as FPGA have improved performance (gate speed and the number of gates) and reconfiguration time. Today , a reconfigurable device can integrate a large-scale processor and complex hard-wired logic. System designers found that they need a high-performance processor for their reconfigurable device based systems. To improve processor performance , a multithreade...
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In today’s computing environments, the concurrent execution of multiple applications/threads is common and multi-cores are very well-suited to handle such workloads. However, they suffer from the fact that any mismatch between the application’s inherent instruction-level parallelism (ILP) and the core’s parallelism leads to unused resources or loss in performance. An accepted solution is to inc...
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For my MSc project at the Computer Engineering Laboratory at Delft University of Technology I will design and implement a reconfigurable Very Large Instruction Word (VLIW) processing core, for use within the Molen[6, 9] reconfigurable processing paradigm. The Instruction Set Architecture (ISA) used for this processing core will be VEX[2] (VLIW Example), which is loosely modeled on the ISA of th...
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ژورنال
عنوان ژورنال: IEEE Access
سال: 2019
ISSN: 2169-3536
DOI: 10.1109/access.2019.2919589